1. Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to improved methods and apparatus for the fabrication of high aspect ratio features of semiconductor devices with high selectivities.
2. Description of the Related Art
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer substrate, which is typically made of silicon. During the fabrication process, various materials are deposited on different layers in order to build a desired IC. Typically, conductive layers, which may include patterned metallization lines, polysilicon transistor gates and the like, are insulated from one another by dielectric materials (e.g., SiO.sub.2, BPSG, PSG, TEOS, etc.). Because semiconductor ICs are fabricated as multi-layered structures, there is a common need to interconnect IC features that are patterned on one layer with IC features of another layer. To accomplish these interconnections, via holes are typically etched through the dielectric materials down to an underlying IC feature.
Once the via holes are etched, the via holes are filled with a conductive material (e.g., tungsten, aluminum, etc.) to establish conductive "vias" between the underlayer and a subsequently deposited and patterned metallization layer. In other cases, via holes are etched down to an underlying polysilicon transistor gate or silicon wafer diffusion regions. Once these vias are etched, the via holes are conductively filled to form electrical "contacts" between the underlying devices and a subsequently deposited and patterned metallization layer.
For ease of discussion, FIG. 1A shows a cross-sectional view of a semiconductor wafer 10 having various deposited and etched layers. As shown, a transistor device including a gate oxide 20, polysilicon gate 22, spacers 24 and diffusion regions 12 is formed over a surface of the semiconductor wafer 10. In general, once the components of the transistor device are formed, a dielectric layer 16 is deposited to a suitable thickness over the device and the semiconductor wafer 10. As mentioned above, via holes are typically required to be etched down to the polysilicon gate 22 and diffusion regions 12, such that appropriate electrical interconnections may be made. In conventional via hole etching techniques, a photoresist layer 18 is applied and then patterned to expose region where via holes will ultimately reside.
Once the photoresist layer 18 is patterned, a combination of fluorocarbons (e.g., CF.sub.4 /CHF.sub.3) gases are used to etch through the dielectric layer 16. Unfortunately, these combinations of fluorocarbon chemistries suffer because they have poor etch-stop characteristics when etching small features with high aspect ratios. To overcome these etch stop issues, O.sub.2 and/or CO chemistries are usually added to the plasma gases. However, when O.sub.2 is added, a substantial amount of the photoresist layer 18 is removed as well as a portion of an underlayer.
Further, when an excessive amount of photoresist layer 18 is removed, a decrease in the thickness from about PR.sub.1 to about PR.sub.2 may occur during via hole etching operations. With a substantial amount of the photoresist layer 18 lost, it is often difficult to achieve good critical dimension (CD) control. In some cases, when the dielectric layer is substantially thick, the photoresist layer 18 may become completely consumed even before the via hole 14b is completely formed.
Although, the commonly used CxFy/CO plasma etch chemistry consumes less photoresist than the CxFy/O.sub.2 plasma chemistry, it has been found to exhaust an excessive amount of toxic by-products during etching operations. Of course, reducing environmental hazards is always a desired aspect of semiconductor manufacturing. As such, when environmentally adverse fabrication chemicals are used, cleaning and disposal costs are also increased.
The conventional plasma etch chemistries therefore exhibit very poor selectivity because a substantial amount of the photoresist layer 18 as well as layers (e.g., polysilicon, silicon, metallization, etc.) that underlie the via hole are excessively etched when the via holes are etched through the dielectric layer 16. As mentioned above and shown in FIG. 1A, an excessive amount of polysilicon material may be removed from the polysilicon gate 22 when via hole 14a is etched, while just enough etching was completed in via hole 14b.
To combat this problem, thicker photoresists 18 are being applied, to ensure that a suitable amount of photoresist material remains over protected regions of the dielectric layer 16. A problem with adding increasingly thicker photoresist layers 18 is that the aspect ratios of the via holes increase. For example, if the width of the via holes stay constant, and the height increases, the aspect ratio (i.e., aspect ratio=height/width) will necessarily increase. Unfortunately, when poor selectivity is coupled with increasing aspect ratios, it is often difficult to achieve good critical dimension (CD) control in semiconductor devices having smaller and smaller dimensions.
Furthermore, a thicker photoresist layer 18 is not practical for small feature applications due to photolithography tool limitations. This is because for smaller features, the wavelengths of the exposed light used in photolithography tools need to be shorter to achieve a better resolution. However, shorter wavelengths suffer in that they have a shallower focus depth. This is further complicated because contact and via holes continue to shrink in size, and the thickness of the photoresist layers are becoming thinner than ever before.
In view of the foregoing, what is needed are improved methods and apparatus for achieving high selectivities without slowing down etching operations through dielectric materials.